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single - lead, heart rate monitor front end dat a sheet AD8232 rev. a document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent ri ghts of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2012 C 2013 analog devices, inc. all rights reserved. technical support www.analog.com features fully integrated single - lead ecg front end low supply current: 1 7 0 a (typical) common - mode rejection ratio: 80 db (dc to 60 hz) two or three electrode configurations high signal gain (g = 100) with dc blocking capabilities 2 - pole adjustable high - pass filter accepts up to 300 mv of half cell potential fast restore feature improves filter settling uncommitted op amp 3 - pole adjustable low - pass filter with a djustable gain lea ds off detection: ac or dc options integrated right leg drive (rld) amplifier single - supply operation: 2.0 v to 3.5 v integrated reference buffer generates virtual ground rail - to - rail output internal rfi filter 8 kv hbm esd rating shutdown pin 20 - lead 4 mm 4 mm lfcsp package applications fitness and activi ty heart rate monitors portable ecg remote health monitors gaming peripherals biopotential signal acquisition functional block dia gram figure 1. general description the AD8232 is an integrated signal conditioning block for ecg and other biopote ntial measurement applications. it is designed to extract, amplify , and filter small biopotential signals in the pres ence of noisy conditions, such as those created by motion or remote electrode placement. this design allows for an ultra low power analog - to - digital converter ( adc ) or an embedded microcontroller to acquire the output signal easily . the AD8232 can implement a two - pole high - pass filter for eliminating motion artifacts and the electrode half - cell potential. this filter is tightly coupled w ith the instrumentation architec - ture of the amplifier to allow both large gain and high - pass filtering in a single stage, thereby saving space and cost. a n uncommitted operational amplifier enables the AD8232 to create a three - pole low - pass filt er to remove additional noise. the user can select the frequency cutoff of all filters to suit different types of applications. to improve common - mode rejectio n of the line frequencies in the system and other undesired interferences, the AD8232 includes an amplifier for driven lead applications, such as righ t leg drive (rld). the AD8232 includes a fast restore function that reduces the duration of otherwise long settling t ails of the high - pass filters. aft er an abrupt signal change that rails the amplifier (such as a leads off condition), the AD8232 automatically adju sts to a higher filter cutoff. this f eature allows the AD8232 to recover quickly, and therefore , to take valid measurements soon after connecting the electrodes to the subject. the AD8232 is available in a 4 mm 4 mm , 20 - lead lfcsp package. performance is specified from 0c to 70c and is operational from ? 40c to + 85c. lod? lod+ AD8232 +v s gnd out opamp? refout o p amp+ sw refin iaout hpsense hpdrive +in ?in rld rldfb fr sdn ac/dc leads-off detection 10k? 10k? 150k? s1 s2 20 2 1 3 4 19 18 17 16 15 ia a3 5 6 7 8 9 a1 10 a2 14 13 12 11 10866-001 c2 c1
AD8232 data sheet rev. a | page 2 of 28 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 5 ? esd caution .................................................................................. 5 ? pin configuration and function descriptions ............................. 6 ? typical performance characteristics ............................................. 7 ? instrumentation amplifier performance curves ..................... 7 ? operational amplifier performance curves .......................... 10 ? right leg drive (rld) amplifier performance curves ....... 13 ? reference buffer performance curves .................................... 14 ? system performance curves ..................................................... 15 ? theory of operation ...................................................................... 16 ? architecture overview .............................................................. 16 ? instrumentation amplifier ........................................................ 16 ? operational amplifier ............................................................... 16 ? right leg drive amplifier ......................................................... 17 ? reference buffer ......................................................................... 17 ? fast restore circuit .................................................................... 17 ? leads off detection ................................................................... 18 ? standby operation ..................................................................... 19 ? input protection ......................................................................... 19 ? radio frequency interference (rfi) ........................................ 20 ? power supply regulation and bypassing ................................ 20 ? input referred offsets ............................................................... 20 ? layout recommendations ........................................................ 20 ? applications information .............................................................. 21 ? eliminating electrode offsets .................................................. 21 ? high-pass filtering .................................................................... 21 ? low-pass filtering and gain ..................................................... 23 ? driving analog-to-digital converters .................................... 23 ? driven electrode ........................................................................ 23 ? application circuits ....................................................................... 24 ? heart rate measurement next to the heart ........................... 24 ? exercise application: heart rate measured at the hands .... 24 ? cardiac monitor configuration ............................................... 25 ? portable cardiac monitor with elimination of motion artifacts ....................................................................................... 25 ? packaging and ordering information ......................................... 27 ? outline dimensions ................................................................... 27 ? ordering guide .......................................................................... 27 ? revision history 2/13rev. 0 to rev. a changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 6 change to figure 17 ......................................................................... 9 changes to figure 22 and figure 25............................................. 11 changes to figure 34 and figure 36............................................. 14 changes to figure 45, architecture overview section, and instrumentation amplifier section .............................................. 17 changes to right leg drive amplifier section, reference buffer section, fast restore circuit section, and figure 48; added figure 46, renumbered sequentially ........................................... 18 changes to figure 49 ...................................................................... 19 changes to ac leads off detection section and standby operation section ........................................................................... 20 changes to input referred offsets section ................................. 21 changes to figure 53 and high-pass filtering section ............. 22 changes to additional high-pass filtering options section; added table 4 ................................................................................. 23 changes to low-pass filtering and gain section; added driving analog-to-digital converters section and figure 61................ 24 changes to figure 62, figure 64, and heart rate measurement next to the heart section .............................................................. 25 changes to exercise application: heart rate measured at the hands and figure 66 ...................................................................... 26 changes to figure 68...................................................................... 27 8/12revision 0: initial version
data sheet AD8232 rev. a | page 3 of 28 specifications v s = 3 v, v ref = 1.5 v, v cm = 1.5 v, t a = 25c, fr=low, sdn=high, ac/ dc = low, unless otherwise noted. table 1 . parameter symbol test conditions/comments min typ max unit instrumentation amplifier common - mode rejection ratio , dc to 60 hz cmrr v cm = 0. 3 5 v to 2. 8 5 v, v diff = 0 v 80 86 db v cm = 0. 3 5 v to 2. 8 5 v, v diff = 0.3 v 80 db power supply rejection ratio psrr v s = 2.0 v to 3.5 v 76 90 db offset voltage (rti) v os instrumentation amplifier inputs 3 8 mv dc blocking input 1 5 50 v average offset drift instrumentation amplifier inputs 10 v/ c dc blocking input 1 0.05 v/ c input bias current i b 50 200 pa t a = 0c to 70c 1 na input offset current i os 25 100 pa t a = 0c to 70c 1 na input impedance differential 10|| 7. 5 g||pf common mode 5 ||1 5 g||pf input voltage noise (rti) spectral noise density f = 1 khz 100 nv/hz peak - to - peak voltage noise f = 0.1 hz to 10 hz 1 2 v p - p f = 0.5 hz to 40 hz 1 4 v p - p input voltage range t a = 0c to 70c 0.2 +v s v dc differential input range v diff ? 300 +300 mv output output swing r l = 5 0 k 0.1 +v s ? 0.1 v short - circuit current i out 6.3 ma gain a v 100 v/v gain error v diff = 0 v 0. 4 % v diff = ? 300 mv to +300 mv 1 3.5 % average gain drift t a = 0c to 70c 12 ppm/ c bandwidth bw 2 khz rfi filter cutoff ( each input ) 1 m hz operational amplifier (a1) offset voltage v os 1 5 mv average tc t a = 0c to 70c 5 v/ c input bias current i b 100 pa t a = 0c to 70c 1 na input offset current i os 100 pa t a = 0c to 70c 1 na input voltage range 0.1 +v s ? 0.1 v common - mode rejection ratio cmrr v cm = 0.5 v to 2.5 v 100 db power supply rejection ratio psrr 100 db large signal voltage gain a vo 110 db output voltage range r l = 50 k 0.1 +v s ? 0.1 v short - circuit current limit i out 12 ma gain bandwidth product gbp 100 khz slew rate sr 0.02 v/s voltage noise density (rti) e n f = 1 khz 60 nv/hz peak - to - peak voltage noise (rti) e n p - p f = 0.1 hz to 10 hz 6 v p - p f = 0.5 hz to 40 hz 8 v p - p
AD8232 data sheet rev. a | page 4 of 28 parameter symbol test conditions/comments min typ max unit right leg drive amplifier (a2) output swing r l = 50 k 0.1 +v s ? 0.1 v short - circuit current i out 11 ma integrator input resistor 120 150 180 k gain bandwidth product gdp 100 khz reference buffer (a3) offset error v os r l > 5 0 k 1 mv input bias current i b 100 pa short - circuit current limit i out 12 ma voltage range r l = 50 k 0.1 +v s ? 0.7 v dc leads off comparators threshold voltage +v s ? 0.5 v hysteresis 6 0 mv propagation delay 0.5 s ac leads off detector square wave frequency f ac 50 100 175 khz square wave amplitude i ac 200 na p - p impedance threshold between +in and ? in 10 20 m detection delay 110 s fast restore circuit switches s1 and s2 on resistance r on 8 10 1 2 k off leakage 1 00 p a window comparator threshold voltage from either rail 50 m v propagation delay 2 s switch timing characteristics feedback recovery switch o n t ime t sw1 110 ms filter recovery switch o n t ime t sw2 55 ms fast restore reset t rst 2 s logic interface input characteristics input voltage (ac/ dc and fr) low v il 1.24 v high v ih 1.35 v input voltage ( sdn ) low v il 2.1 v high v ih 0.5 v output characteristics lod+ and lod? terminals output voltage low v ol 0.05 v high v oh 2.95 v system specifications quiescent supply curren t 1 7 0 230 a t a = 0c to 70 c 210 a shutdown current 40 500 na t a = 0c to 70 c 100 n a supply range 2.0 3.5 v specified temperature range 0 70 c operational temperature range ?40 +85 c 1 offset referred to the input of the instrumentation amplifier inputs. se e th e input referred offsets section for additional information .
data sheet AD8232 rev. a | page 5 of 28 absolute maximum rat ings table 2 . parameter rating supply voltage 3.6 v output short - circuit current duration indefinite maximum voltage , any terminal 1 +v s + 0.3 v minimum voltage , any terminal 1 ? 0.3 v storage temperature range ? 65 c to +1 25c operating temperature range ? 40c to + 8 5 c max imum junction temperature 1 4 0c ja thermal impedance 2 48 c/w jc thermal impedance 4.4 c/w esd rating human body model (hbm) 8 kv charged device model (ficdm) 1.25 kv machine model (mm) 200 v 1 this level or the maximum specified supply voltage, whichever is the lesser, indicates the superior voltage limit for any terminal. if input voltages beyond the specified minimum or maximum voltages are expected, place resistors in series with the inputs to limit the current to less than 5 ma. 2 ja is specified for a device in free air on a 4 - layer jedec board. esd caution s t r e s s es a b o ve t h o s e l i s t e d u n d e r a b s o l u t e m a x i m um r a t i n gs m a y c a u s e p e r m a n e n t dam a g e t o t h e d e v i c e . this is a s t r e s s r a t i n g o n l y ; fu n c t i o n a l o p e r a t i o n o f t h e d ev i c e a t t h e s e o r a n y o t h e r co n d i t i o ns a b o ve t h o s e indi c a t e d i n t h e o p e r a t i o na l s e c t i o n o f t h is s p e c i fi c a t ion is n o t i m p l i e d . e x p o su r e t o a b s o l u te ma x i m u m r a t in g c o n d i t i o n s fo r e x t e n d e d p e r i o d s m a y a ff e c t d e vi c e r e l i a b i l i t y .
AD8232 data sheet rev. a | page 6 of 28 pin configuration and function descripti ons figure 2 . pin configuration table 3 . pin function descriptions pin no. mnemonic description 1 hpdrive high - pass driver output . connect hpdrive to the capacitor in the first high - pass filter. the AD8232 d rives this pin to keep hp sense at the same level as the reference voltage. 2 +in instrumentation amplifier positive input . +in is t ypically connected to the left arm (la) electrode. 3 ?in instrumentation amplifier negative input . ?in is t ypically connected to the right arm (ra) electrode. 4 rldfb right leg drive feedback input . rldfb is the f eedback terminal for the right leg drive circuit. 5 rld right leg drive output. connect the driven electrode (typically , right leg) to th e rld pin. 6 sw fast restore switch terminal . connect this terminal to the output of the second high - pass filter. 7 opamp+ operational amplifier noninverting input . 8 refout r eference b uffer o utput . the instrumentation amplifier output is referenced to this potential. use refout as a virtual ground for any point in the circuit that needs a signal reference. 9 opamp ? operational amplifier inverting input . 10 out operational amplifier output. the fully conditioned heart rate signal is present at this output . out can be connected to the input of an adc . 11 lod ? leads off comparator output . in dc leads off detection mode , lod ? is high when the electrode to ? in is disconnected , and it is l ow when co nnected. in ac leads off detection mode , lod ? is always low. 12 lod+ leads off comparator output . in dc leads off detection mode , lod+ is high when the +in electrode is disconnected , and it is l ow when connected. in ac leads off detection mode , lod+ is high when either the ? in or +in electrode is disconnected , and it is low when both electrodes are connected. 13 sdn shutdown c ontrol input . drive sdn low to enter the low power shut down mode. 14 ac/ dc leads off mode control input . drive the ac/ dc pin low for dc leads off mode. drive the ac/ dc pin high for ac leads off mode. 15 fr fast restore control input . drive fr high to enable fast recovery mode ; o therwise, drive it low. 16 gnd power supply ground . 17 +v s power supply terminal . 18 refin reference buffer input. use refin, a high impedance input terminal , to set the level of the reference buffer. 19 iaout instrumentation amplifier output terminal . 20 hpsense high - pass sense input f or instrumentation amplifier. connect hpsense to the junction of r and c that sets the corner frequency of the dc blocking circuit . ep exposed pad. connect the exposed pad to gnd or leave it unconnected. 14 13 12 1 3 4 ac/dc 15 fr sdn lod+ 11 lod? hpdrive ?in 2 +in rldfb 5 rld 7 opamp+ 6 sw 8 refout 9 opamp? 10 out 19 iaout 20 hpsense 18 refin 17 +v s 16 gnd AD8232 top view notes 1. connect the exposed pad to gnd or leave unconnected. 10866-002
data sheet AD8232 rev. a | page 7 of 28 typical performance characte ristics v s = 3 v, v ref = 1.5 v, v cm = 1.5 v, t a = 25 c , unless otherwise noted . instrumentation ampl ifier performance cu rves figure 3 . instrumentation a mplifier cmrr d istribution figure 4 . instrumentation amplifier gain error distribution figure 5 . instrumentation amplifier input common - mode range vs. output voltage figure 6 . instrumentation amplifier input bias current vs. cmv figure 7 . instrumentation amplifier gain vs. frequency figure 8 . instrumentation amplifier cmrr vs. frequency, rti 1200 1000 200 400 600 800 0 ?120 ?90 90 60 30 0 ?60 ?30 120 units cmrr (v/v) 10866-003 1400 1200 1000 200 400 600 800 0 ?2.0 ?1.5 1.5 1.0 0.5 0 ?1.0 ?0.5 2.0 units gain error (%) 10866-004 3.5 3.0 ?0.5 0 0.5 1.0 1.5 2.0 2.5 0 0.5 1.0 3.5 3.0 2.5 2.0 1.5 input common-mode voltage (v) output voltage (v) 10866-005 50 ?50 0 0.5 1.0 3.5 3.0 2.5 2.0 1.5 input bias current (pa) input common-mode voltage (v) ?40 ?30 ?20 ?10 0 10 20 30 40 10866-006 50 40 30 20 10 0 ?10 1 100k 10k 1k 100 10 gain (db) frequency (hz) no dc offset 300mv offset 10866-007 120 100 40 60 80 20 10 100k 10k 1k 100 cmrr (db) frequency (hz) no dc offset +300mv offset ?300mv offset 10866-008
AD8232 data sheet rev. a | page 8 of 28 figure 9 . instrumentation amplifier psrr vs. frequency figure 10 . instrumentation amplifier voltage noise spectral density (rti) figure 11 . instrumentation amplifier 0.1 hz to 10 hz noise figure 12 . instrumentation ampli fier 0.5 hz to 40 hz noise figure 13 . instrumentation amplifier gain error vs. dc offset figure 14 . instrumentation amplifier small signal pulse response 120 20 0.1 1 10 100k 10k 1k 100 psrr (db) frequency (hz) 30 40 50 60 70 80 90 100 110 10866-009 10k 1k 100 1 0.1 1 10 100k 10k 1k 100 noise (nv/hz) frequency (hz) 10866-010 10v/div 1s/div 10866-0 1 1 10v/div 200ms/div 10866-012 1.0 0 0 50 300 250 200 150 100 gain error (%) dc offset (mv) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10866-013 50mv/div 100s/div 22pf 470pf 1nf 10866-014
data sheet AD8232 rev. a | page 9 of 28 figure 15. instrumentation amplifier large signal pulse response figure 16. instrumentation amplifier output swing vs. load figure 17. instrumentation amplifier dc blocking input offset drift figure 18. instrumentation amplifier input bias current and input o ffset current vs. temperature figure 19. instrumentation amplifier gain error vs. temperature figure 20. instrumentation amplifier cmrr vs. temperature 100s/div 0.5v/div 10866-015 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output swing (v) load ( ? ) ?40-c +25c +85c 10866-016 0.4 ?0.4 ?40?20 0 204060 100 80 dc blocking input offset (mv) temperature (c) ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 10866-017 4.0 ?1.0 ?40 ?20 ?0 20 40 60 80 100 input bias current (na) input offset current (na) temperature (c) ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 ?0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 i b i os 10866-018 0.5 ?0.5 ?40 ?20 0 100 80 60 40 20 gain error (%) temperature (c) ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 10866-019 50 ?50 ?40 ?20 0 100 80 60 40 20 cmrr (v/v) temperature (c) ?40 ?30 ?20 ?10 0 10 20 30 40 10866-020
AD8232 data sheet rev. a | page 10 of 28 operational amplifie r performance curves figure 21 . operational amplifier offset distribution figure 22 . operational amplifier open - loop gain and phase vs. frequency figure 23 . operational amplifier small signal response for various capacitive loads figure 24 . operational amplifier large signal transient response figure 25. operational amplifier voltage spectral noise density vs. frequency figure 26 . operational amplifier 0.1 hz to 10 hz noise 1000 200 400 600 800 0 ?4 ?2 0 4 2 units offset voltage (mv) 10866-021 140 ?40 180 0 0.1 1m 100k 10k 1k 100 10 1 gain (db) phase margin (degrees) frequency (hz) 20 40 60 80 100 120 140 160 ?20 0 20 40 60 80 100 120 gain phase margin 10866-022 50mv/div 10s/div 22pf 470pf 1nf 10866-023 100v/div 0.5v/div 10866-024 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 noise (nv/hz) frequency (hz) 10866-025 5v/div 1s/div 10866-026
data sheet AD8232 rev. a | page 11 of 28 figure 27 . operational a mplifier 0.5 hz to 40 hz noise figure 28 . operational amplifier bias current vs. input common - mode voltage figure 29 . operational amplifier output voltage swing vs. output current figure 30 . operational amplif ier power supply rejection ratio figure 31 . operational amplifier load transient response (100 a load change ) figure 32 . operational amplifier offset vs. temperature 5v/div 200ms/div 10866-027 100 ?100 0 3.5 input bias current (pa) input common-mode voltage (v) ?80 ?60 ?40 ?20 0 20 40 60 80 0.5 1.0 1.5 2.0 2.5 3.0 10866-028 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output swing (v) load (?) ?40- c +25c +85c 10866-029 120 0 10 20 0.1 1 10 100k 10k 1k 100 psrr (db) frequency (hz) 30 40 50 60 70 80 90 100 110 10866-030 20v/div 10v/div 10866-031 0.8 ?0.8 ?40 ?20 0 20 40 60 100 80 offset (mv) temperature (c) ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 10866-032
AD8232 data sheet rev. a | page 12 of 28 figure 33 . operational amplifier bias current vs. temperature 10,000 1,000 100 10 1 ?40 100 input bias current (pa) temperature (c) ?20 0 20 40 60 80 10866-033
data sheet AD8232 rev. a | page 13 of 28 right leg drive (rld) amplifier performanc e curves figure 34 . rld amplifier open - loop gain and phase vs. frequency figure 35 . rld amplifier output voltage swing vs. output current figure 36 . rld amplifier voltage spectral noise density vs. frequency figure 37 . rld amplifier 0.1 hz to 10 hz noise figure 38 . rld a mplifier 0.5 hz to 40 hz noise 140 ?40 180 0 0.01 1m 100k 10k 1k 100 10 1 0.1 open-loop gain (db) phase (degrees) frequency (hz) 20 40 60 80 100 120 140 160 ?20 0 20 40 60 80 100 120 10866-034 gain phase 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 100 1m 100k 10k 1k output swing (v) load (?) ?40- c +25c +85c 10866-035 10k 1k 100 10 0.1 1 10 100k 10k 1k 100 noise (nv/hz) frequency (hz) 10866-036 5v/div 1s/div 10866-037 5v/div 200ms/div 10866-038
AD8232 data sheet rev. a | page 14 of 28 reference buffer per formance curves figure 39 . reference buffer load regulation figure 40 . reference buffer load transient response (100 a load change ) figure 41 . reference buffer output impedance vs. frequency figure 42 . reference buffer bias current vs. temperature 20 ?20 0.01 10 1 0.10 output error (mv) load current (ma) 10866-039 ?15 ?10 ?5 0 5 10 15 source sink 20mv/div 10s/div 10866-040 10,000.0 1,000.0 1.0 10.0 100.0 0.1 0.1 1 10 100k 10k 1k 100 output impedance (?) frequency (hz) 10866-041 1000 100 10 1 ?40 100 input bias current (pa) temperature (c) 10866-042 ?20 20 0 40 60 80
data sheet AD8232 rev. a | page 15 of 28 system performance curves figure 43 . supply current vs. temperature figure 44 . shutdown current vs. temperature 240 100 ?40 100 supply current (a) temperature (c) 10866-043 ?20 20 0 40 60 80 120 140 160 180 200 220 v s = 2v v s = 3v v s = 3.5v 200 0 ?40 100 shutdown current (na) temperature (c) 10866-044 ?20 20 0 40 60 80 v s = 2v v s = 3v v s = 3.5v 20 40 60 80 100 120 140 160 180
AD8232 data sheet rev. a | page 16 of 28 theory of operation figure 45. simplified schematic diagram architecture overview the AD8232 is an integrated front end for signal conditioning of cardiac biopotentials for heart rate monitoring. it consists of a specialized instrumentation amplifier (ia), an operational amplifier (a1), a right leg drive amplifier (a2), and a midsupply reference buffer (a3). in addition, the AD8232 includes leads off detection circuitry and an automatic fast restore circuit that brings back the signal shortly after leads are reconnected. the AD8232 contains a specialized instrumentation amplifier that amplifies the ecg signal while rejecting the electrode half-cell potential on the same stage. this is possible with an indirect current feedback architecture, which reduces size and power compared with traditional implementations instrumentation amplifier the instrumentation amplifier is shown in figure 45 as comprised by two well-matched transconductance amplifiers (gm1 and gm2), the dc blocking amplifier (hpa), and an integrator formed by c1 and an op amp. the transconductance amplifier, gm1, generates a current that is proportional to the voltage present at its inputs. when the feedback is satisfied, an equal voltage appears across the inputs of the transconductance amplifier, gm2, thereby matching the current generated by gm1. the difference generates an error current that is integrated across capacitor c1. the resulting voltage appears at the output of the instrumentation amplifier. the feedback of the amplifier is applied via gm2 through two separate paths: the two resistors divide the output signal to set an overall gain of 100, whereas the dc blocking amplifier integrates any deviation from the reference level. consequently, dc offsets as large as 300 mv across the gm1 inputs appear inverted and with the same magnitude across the inputs of gm2, all without saturating the signal of interest. to increase the common-mode voltage range of the instrumen- tation amplifier, a charge pump boosts the supply voltage for the two transconductance amplifiers. this further prevents saturation of the amplifier in the presence of large common-mode signals, such as line interference. the charge pump runs from an internal oscillator, the frequency of which is set around 500 khz. operational amplifier this general-purpose operational amplifier (a1) is a rail-to-rail device that can be used for low-pass filtering and to add additional gain. the following sections provide details and example circuits that use this amplifier. 10k ? iaou t hpsense hpdrive s1 gm1 gm2 99r r +v s 0.7v instrumentation amplifier (ia) +v ? 0.05v s 0.05v refout refin ?in +in fr v cm c1 lod+ lod? +v ? 0.5v s sw op a mp+ opamp? out rld rldfb gnd 150k ? 10k ? hpa +v s = refout charge pump synch rectifier switch timing a3 a2 a1 ac/dc ac/dc ac/dc ac/dc sdn s1 s2 s2 19 2 3 4 5 18 6 7 9 10 1 20 15 14 13 11 12 17 16 8 *all switches shown in dc leads-off detection position and fast restore disabled 10866-045 rfi filter
data sheet AD8232 rev. a | page 17 of 28 right leg drive amplifier th e right leg drive (rld) amplifier inverts the com mon - mode signal that is present at the instrumentation amplifier inputs. when the right leg drive output current is injected into the subject, it counteract s common - mode voltage variations, thus improving the common - mode rejection of the system . the common - mode signal that is present across the inputs of the instrumentation amplifier is derived from the transconduct - ance amplifier , gm1. it is then connected to the inverting input of a2 through a 150 k resistor. an integrator can be built by connecting a c apacitor between the rld fb and rld terminals. a good starting point is a 1 nf capacitor, which place s the crossover frequency at about 1 khz (the frequency at which the amplifier has an inverting unity gain). this configuration result s in about 26 db of l oop gain available at a frequency range from 50 hz to 60 hz for common - mode line rejection. higher capacitor values reduce the crossover frequency, th e reby reducing the gain that is available for rejection and, consequently, increasing the line noise. lower capacitor values move the crossover frequency to higher frequencies, allowing increased gain. the tradeoff is that with higher gain, the system can become unstable and saturate the output of the right leg amplifier. note that when using this amplifi er to drive an electrode, there should be a resistor in series with the output to limit the current to be always less than 10ua even in fault conditions. for example, if the supply used is 3.0v, this resistor should be greater than 330k to account for com ponent and supply variations. figure 46 . typical configuration of right - leg drive circuit in two - electrode configurations, rld can be used to bias the inputs through 10m resistors as described in the leads off detection section. if left unused, it is recommended to configure a2 as a follower by connecting rldfb directly to rld. reference buffer the AD8232 operate s from a sing le supply. to simplify the design of single - supply applications, the AD8232 includes a reference buffer to create a virtual ground between the supply v oltage and the system ground. the signals present at the out - put of the instrumentation amplifier are r eferenced around this voltage. for example, if there is zero differential input voltage, the voltage at the output of the instrumentation amplifier is th is reference voltage. the reference voltage level is set at the ref in pin. it can be set with a voltage divider or by driving the refi n pin from some other point in the circuit (f or example , from the adc reference ). the voltage is available at the ref out pin for the filtering circuits or for an adc input . figure 47 . setting the internal reference to limit the power consumption of the voltage divider, the use of large resistors is recommended, such as 10 m . the designer must keep in mind that high resistor values make it easier for interfering signals to appear at the input of the reference buffer. to minim ize noise pickup, it is recommended to place the resistors close to each other and as near as possible to the refin termin al . furthermore, use a capacitor in parallel with the lower resistor on the divider for additional filtering, as shown in figure 47. keep in mind that a large capacito r result s in better noise fil tering but it take s longer to settle the reference after power - up. the total time it take s the reference to settle within 1% can be estimated with the formula r2 r1 c1 r2 r1 t reference settle + = 5 _ note that disabling the AD8232 with the shutdown terminal does not discharge this capacitor. fast restore circuit because of the low cutoff frequency used in high - pass filters i n ecg applications, signals may requi re several seconds to settle. this settling time can result in a frustrating delay for t he user after a step response: for example, when the electrodes are first connected. this fast restore function is implemented inte rnally, as shown in figure 48 . the output of the instrumentation amplifier is conne c - ted t o a window comparator. the window comparator detect s a saturation condition at the output of the instrumentation amplifier when its voltage approaches 5 0 mv from either supply rail. figure 48 . fast restore circuit rld 1nf r* *limit current t o less than 10 a. rldfb a2 refout t o driven electrode 150k ? v cm 18 5 4 10866-146 refin a3 18 r 1 r 2 c 1 +v s 10866-046 switch timing s1 s2 lod+ lod? fr 15 iaout 0.05v +in ?in ia 2 3 +v s ? 0.05v 10866-047
AD8232 data sheet rev. a | page 18 of 28 figure 49. timing diagram for fast restore switches (time base not to scale) if this saturation condition is present when both input electrodes are attached to the subject, the comparator triggers a timing circuit that automatically closes switch s1 and switch s2 (see figure 49 for a timing diagram). these two switches (s1 and s2) enable two different 10 k resistor paths: one between hpsense and iaout and another between sw and refout. during the time switch s1 and switch s2 are enabled, these internal resistors appear in parallel with their corresponding external resistors forming high-pass filters. the result is that the equivalent lower resistance shifts the pole to a higher frequency, delivering a quicker settling time. note that the fast restore settling time depends on how quickly the internal 10 k resistors of the AD8232 can drain the capacitors in the high-pass circuit. smaller capacitor values result in a shorter settling time. if, by the end of the timing, the saturation condition persists, the cycle repeats. otherwise, the AD8232 returns to its normal operation. if either of the leads off comparator outputs is indi- cating that an electrode has been disconnected, the timing circuit is prevented from triggering because it is assumed that no valid signal is present. to disable fast restore, drive the fr pin low or tie it permanently to gnd. leads off detection the AD8232 includes leads off detection. it features ac and dc detection modes optimized for either two- or three-electrode configurations, respectively. dc leads off detection the dc leads off detection mode is used in three-electrode con- figurations only. it works by sensing when either instrumentation amplifier input voltage is within 0.5 v from the positive rail. in this case, each input must have a pull-up resistor connected to the positive supply. during normal operation, the subjects potential must be inside the common-mode range of the instrumentation amplifier, which is only possible if a third electrode is connected to the output of the right leg drive amplifier. figure 50. circuit configuration for dc leads off detection because in dc leads off mode the AD8232 checks each input individually, it is possible to indicate which electrode is discon- nected. the AD8232 indicates which electrode is disconnected by setting the corresponding lod? or lod+ pin high. to use this mode, connect the ac/ dc pin to ground. leads off leads on s1 s2 saturation detected no saturation t s1 t s2 t rst 10866-048 rld 10m ? 10m ? to driven electrode ia 2 3 5 + v s 10866-049
data sheet AD8232 rev. a | page 19 of 28 ac leads off detection the ac leads off detection mode is useful when using two electrodes only (it does not require the use of a driven electrode). in this case, a conduction path must exist between the two electrodes, which is usually formed by two resistors, as shown in figure 51. these resistors also provide a path for bias return on each input. connect each resistor to refout or rld to maintain the inputs within the common-mode range of the instrumentation amplifier. figure 51. circuit configuration for ac leads off detection the AD8232 detects when an electrode is disconnected by forcing a small 100 khz current into the input terminals. this current flows through the external resistors from in+ to in? and develops a differential voltage across the inputs, which is then synchronously detected and compared to an internal threshold. the recommended value for these external resistors is 10 m. low resistance values make the differential drop too low to be detected and lower the input impedance of the amplifier. when the electrodes are attached to the subject, the impedance of this path should be less than 3 m to maintain the drop below the comparators threshold. as opposed to the dc leads off detection mode, the AD8232 is able to determine only that an electrode has lost its connection, not which one. during such an event, the lod+ pin goes high. in this mode, the lod? pin is not used and remains in a logic low state. to use the ac leads off mode, tie the ac/ dc pin to the positive supply rail. note that while refout is at a constant voltage value, using the rld output as the input bias may be more effective in rejecting common-mode interference. standby operation the AD8232 includes a shutdown pin ( sdn ) that further enhances the flexibility and ease of use in portable applications where power consumption is critical. a logic level signal can be applied to this pin to switch to shutdown mode, even when the supply is still on. driving the sdn pin low places the AD8232 in shutdown mode and draws less than 200 na of supply current, offering considerable power savings. to enter normal operation, drive sdn high; when not using this feature, permanently tie sdn to +v s . during shutdown operation, the AD8232 is not able to maintain the refout voltage, but it does not drain the refin voltage, thereby maintaining this additional conduction path from the supply to ground. when emerging from a shutdown condition, the charge stored in the capacitors on the high-pass filters can saturate the instru- mentation amplifier and subsequent stages. the use of the fast restore feature helps reduce the recovery time and, therefore, minimize on time in power sensitive applications. input protection all terminals of the AD8232 are protected against esd. in addition, the input structure allows for dc overload conditions that are a diode drop above the positive supply and a diode drop below the negative supply. voltages beyond a diode drop of the supplies cause the esd diodes to conduct and enable current to flow through the diode. therefore, use an external resistor in series with each of the inputs to limit current for voltages beyond the supplies. in either scenario, the AD8232 safely handles a continuous 5 ma current at room temperature. for applications where the AD8232 encounters extreme over- load voltages, such as in cardiac defibrillators, use external series resistors and gas discharge tubes (gdt). neon lamps are com- monly used as an inexpensive alternative to gdts. these devices can handle the application of large voltages but do not maintain the voltage below the absolute maximum ratings for the AD8232. a complete solution includes further clamping to either supply using additional resistors and low leakage diode clamps, such as bav199 or fjh1100. as a safety measure, place a resistor between the input pin and the electrode that is connected to the subject to ensure that the current flow never exceeds 10 a. calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 a. refout 10m ? 10m ? ia 2 3 17 8 + v s 10866-050
AD8232 data sheet rev. a | page 20 of 28 radio fr equency interference ( rfi ) radio frequency (rf) rectification is often a problem in applications where there are large rf signals. the problem appears as a dc offset voltage at the output . the AD8232 has a 1 5 pf gate capacitance and 10 k resistors at each input. this form s a low - pass filter on each input that reduces rectification at high frequency (see figure 53 ) without the addition of external elements. figure 52 . rfi filter without external capacitors for increased filtering, additional resistors can be added in series with each input. they mu st be placed as close as possible to the instrumentation amplifier inputs. these can be the same resistors used for overload and patient protection. power supply regulat ion a nd bypassing the AD8232 is designed to be powered directly from a single 3 v battery, such as cr2032 type. it can also operate from rechargeable lithium - ion batteries, but the designer must take into account that the voltage during a charge cycle may exceed the absolute maximum ratings of the AD8232 . to avoid damage to the part, use a power switch or a low power, low dropout regulator , such as adp150 . in addition, excessive noise on the supply pins can adversely affect performance. as in all linear circuits, bypass capacitors must be used to decouple the chip power supplies. place a 0.1 f capacit or close to the supply pin. a 1 f capacitor can be used farther away from the part. in most cases, the capacitor can be shared by other integrated circuits. keep in mind that excessive decoupling capacitance increases power dissipation during power cycling. input referred offsets because of its internal architecture, the instrumentation amplifier should be used always with the dc blocking amplifier, shown as hpa in figure 45. as described in the theory of operation section, the dc blocking amplifier attenuates the input referred o ffsets present at the inputs of the instrumentation amplifier. however, this is true only when the dc blocking amplifier is used as an integrator. in this configuration, the input offsets from the dc blocking amplifier dominate appear directly at the outpu t of the instrumentation amplifier. if the dc blocking amplifier is used as a follower instead of its intended function as an integrator, the input referred offsets of the in - amp a re amplified by a factor of 100 . layout recommendatio ns it is important to follow good layout practices to optimize system performance. in low power applications, most resistors are of a high value to minimize additional supply current. the challenge of using high value resistors is that high impedance nodes be come even more susceptible to noise pickup and board parasitics, such as capacitance and surface leakages. k eep all of the connections between high impeda nce nodes as short as possible to avoid introducing additional noise and errors from corrupting the si gnal. to maintain high cmrr over frequency , keep the input traces symmetrical and length matched. place safety and input bias resistors in the same position relative to each input. in addition, t he use of a ground plane significantly improve s th e noise rej ection of the system. AD8232 c g c g iaout +in ?in 10k? 10k? 10866-151
data sheet AD8232 rev. a | page 21 of 28 applications information eliminating electrode offsets the instrumentation amplifier in the AD8232 is designed to apply gain and to filter out near dc signals simultaneously. this capability allows it to amplify a small ecg signal by a factor of 100 yet reject electrode offsets as large as 300 mv. to achieve offset rejection, connect an rc network between the output of the instrumentation amplifier, hpsense, and hpdrive, as shown in figure 53. figure 53. eliminating electrode offsets this rc network forms an integrator that feeds any near dc signals back into the instrumentation amplifier, thus eliminating the offsets without saturating any node and maintaining high signal gain. in addition to blocking offsets present across the inputs of the instrumentation amplifier, this integrator also works as a high- pass filter that minimizes the effect of slow moving signals, such as baseline wander. the cutoff frequency of the filter is given by the equation rc f db ? 2 100 3 ? ? where r is in ohms and c is in farads. note that the filter cutoff is 100 times higher than is typically expected from a single-pole filter. because of the feedback architecture of the instrumentation amplifier, the typical filter cutoff equation is modified by the gain of 100 of the instrumentation amplifier. figure 54. frequency response of single-pole dc blocking circuit just like with any high-pass filter with low frequency cutoff, any fast change in dc offset takes a long time to settle. if such change saturates the instrumentation amplifier output, the s1 switch briefly enables the 10 k resistor path, thus moving the cutoff frequency to )10(2 )10(100 4 4 3 rc r f db ? ? ? ? (1) for values of r greater than 100 k, the expression in equation 1 can be approximated by c f db ? 200 1 3 ? ? this higher cutoff reduces the settling time and enables faster recovery of the ecg signal. for more information, see the fast restore circuit section. high-pass filtering the AD8232 can implement higher order high-pass filters. a higher filter order yields better artifact rejection but at a cost of increased signal distortion and more passive components on the printed circuit board (pcb). two-pole high-pass filter a two-pole architecture can be implemented by adding a simple ac coupling rc at the output of the instrumentation amplifier, as shown in figure 55. figure 55. schematic for a two-pole high-pass filter note that the right side of c2 connects to the sw terminal. just like s1, s2 reduces the recovery time for this ac coupling network by placing 10 k in parallel with r2. see the fast restore circuit section for additional details on switch timing and trigger conditions. keep in mind that if this passive network is not buffered, it exhibits higher output impedance at the input of a subsequent low-pass filter, such as with sallen-key filter topologies. careful component selection can yield good results without a buffer. see the low-pass filtering and gain section for additional information on component selection. 10k ? iaout hpsense hpdrive s1 gm1 gm2 99r r in+ in? v cm h p a electrode offsets c r = refout 19 3 1 20 2 c1 10866-253 50 40 10 20 30 0 0.01 100 10 1 0.1 magnitude (db) frequency (hz) 10866-153 20db per decade 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k ? s2 6 refout 8 to next stage = refout 19 3 1 20 2 c1 c2 r1 r2 10866-053
AD8232 data sheet rev. a | page 22 of 28 additional high-pass filtering options in addition to the topologies explained in the previous sections, an additional pole may be added to the dc blocking circuit for additional rejection of low frequency signals. this configuration is shown in figure 56. figure 56. schematic for an alternative two-pole high-pass filter an extra benefit of this circuit topology is that it allows lower cutoff frequency with lower r and c values and the resistor, r comp , can be used to control the q of the filter to achieve narrow band-pass filters (for heart rate detection) or maximum pass- band flatness (for cardiac monitoring). with this topology, the filter attenuation reverts to a single pole roll off at very low frequencies. because the initial roll off was 40 db per decade, this reversion to 20 db per decade has little impact on the ability of the filter to reject out-of-band low frequency signals. the designer may choose different values to achieve the desired filter performance. to simplify the design process, use the following recommendations as a starting point for component value selection. r1 = r2 100 k c1 = c2 r comp = 0.14 r1 the cutoff frequency is located at c2r2c1r1 f c ? 2 10 ? the selection of r comp to be 0.14 times the value of the other two resistors optimizes the filter for a maximally flat pass band. reduce its value to increase the q and, consequently, the peaking of the filter. keep in mind that a very low value of r comp can result in an unstable circuit. the selection of values based on these criteria result in a transfer function similar to the one shown in figure 58. when additional low frequency rejection is desired, a high-order high-pass filter can be implemented by adding an ac coupling network at the output of the instrumentation amplifier, as shown in figure 57. the sw terminal is connected to the ac coupling network to obtain the best settling time response when fast restore engages. figure 57. schematic for a three-pole high-pass filter figure 58. frequency response of circuits in figure 56 and figure 57 careful analysis and adjustment of all of the component values in practice is recommended to optimize the filter characteristics. a useful hint is to reduce the value of r comp to increase the peaking of the active filter to overcome the additional roll off introduced by the ac coupling network. proper adjustment can yield the best pass-band flatness. the design of the high-pass filter involves tradeoffs between signal distortion, component count, low frequency rejection, and component sizes. for example, a single-pole high-pass filter results in the least distortion to the signal, but its rejection of low-frequency artifacts is the lowest table 4 compares the recommended filtering options. table 4. comparison of high-pass filtering options filter order component count low frequency reje ction capacitor sizes/va lues signal distortion 1 output impedance 2 figure 53 1 2 good large low low figure 55 2 4 better large medium higher figure 56 2 5 better smaller medium low figure 57 3 7 best smaller highest higher 1 for equivalent corner frequency location. 2 output impedance refers to the drive capability of the high-pass filter before the low-pass filter. low output impedance is de sirable to allow flexibility in the selection of values for a low-pass filter, as explained in the low-pass filtering and gain section. 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k? s2 6 refout 8 to next stage = refout 19 3 1 20 2 c1 r1 r2 r comp c2 10866-155 10k ? iaout hpsense hpdrive s1 +in ?in hpa sw 10k ? s2 6 refout 8 to next stage = refout 19 3 1 20 2 c1 c3 r1 r2 r comp c2 r3 10866-156 60 40 20 0 ?20 ?40 ?60 0.01 100 10 1 0.1 magnitude (db) frequency (hz) 10866-157 three-pole filter two-pole filter 40db per decade 40db per decade 20db per decade 60db per decade
data sheet AD8232 rev. a | page 23 of 28 low-pass filtering and gain the AD8232 includes an uncommitted op amp that can be used for extra gain and filtering. for applications that do not require a high-order filter, a simple rc low-pass filter should suffice, and the op amp can buffer or further amplify the signal. figure 59. schematic for a single-pole low-pass filter and additional gain applications that require a steeper roll off or a sharper cut off, a sallen-key filter topology can be implemented, as shown in figure 60. figure 60. schematic for a two-pole low-pass filter the following equations describe the low-pass cut off frequency, gain, and q: f c = 1/(2( r1 c1 r2 c2 )) gain = 1 + r3 / r4 ?? gainc1r1cr2c2r1 c2r2c1r1 q ?????? ??? ? 12 note that changing the gain has an effect on q and vice versa. common values for q are 0.5 to avoid peaking or 0.7 for maximum flatness and sharp cut off. a high value of q can be used in narrow-band applications to increase peaking and the selectivity of the band-pass filter. a common design procedure is to set r1 = r2 = r and c1 = c2 = c, which simplifies the expressions for cutoff frequency and q to f c = 1/(2 rc ) gain q ? ? 3 1 note that q can be controlled by setting the gain with r3 and r4; however, this limits the gain to be less than 3. for gain values equal to or greater than 3, the circuit becomes unstable. a simple modification that allows higher gains is to make the value of c2 at least four times larger than c1. it is important to note that these design equations only hold true in the case that the output impedance of the previous stage is much lower than the input impedance of the sallen-key filter. this is not the case when using an ac coupling network between the instrumentation amplifier output and the input of the low- pass filter without a buffer. to connect these two filtering stages properly without a buffer, make the value of r1 at least ten times larger than the resistor of the ac coupling network (labeled as r2 in figure 55). driving analog-to-digital converters the ability of AD8232 to drive capacitive loads makes it ideal to drive an adc without the need for an additional buffer. however, depending on the input architecture of the adc, a simple low- pass rc network may be required to decouple the transients from the switched-capacitor input typical of modern adcs. this rc network also acts as an additional filter that can help reduce noise and aliasing. follow the recommended guidelines from the adc data sheet for the selection of proper r and c values. figure 61. driving an adc driven electrode a driven lead (or reference electrode) is often used to minimize the effects of common-mode voltages induced by the power line and other interfering sources. the AD8232 extracts the common- mode voltage from the instrumentation amplifier inputs and makes it available through the rld amplifier to drive an opposing signal into the patient. this functionality maintains the voltage between the patient and the AD8232 at a near constant, greatly improving the common-mode rejection ratio. as a safety measure, place a resistor between the rld pin and the electrode connected to the subject to ensure that current flow never exceeds 10 a. calculate the value of this resistor to be equal to the supply voltage across the AD8232 divided by 10 a. the AD8232 implements an integrator formed by an internal 150 k resistor and an external capacitor to drive this electrode. choice of the integrator capacitor is a tradeoff between line rejec- tion capability and stability. the capacitor should be small to maintain as much loop gain as possible, around 50 hz and 60 hz, which are typical line frequencies. for stability, the gain of the integrator should be less than unity at the frequency of any other poles in the loop, such as those formed by the patients capacitance and the safety resistors. the suggested application circuits use a 1 nf capacitor, which results in a loop gain of about 20 at line frequencies, with a crossover frequency of about 1 khz. in a two-lead configuration, the rld amplifier can be used to drive the bias current resistors on the inputs. although not as effective as a true driven electrode, this configuration can provide some common-mode rejection improvement if the sense electrode impedance is small and well matched. refout filtered signal a1 from in-amp stage c r 10866-158 refout filtered signal a1 from in-amp stage c2 c1 r2 r3 r4 10866-159 r1 a1 c r adc 10 AD8232 10866-261
AD8232 data sheet rev. a | page 24 of 28 application circuits heart rate measureme nt next to the heart for wearable exercise devices, the AD8232 is typically p laced in a pod near the heart. the two sense elect rodes are placed under - neath t he pectoral muscles ; no driven electrode is used . b ecause the distance from the heart to the AD8232 is small, the heart signal is strong and there is less muscle artifact interference. in this config uration, space is at a premium. by using as few external components as possible, the circuit in figure 62 is optimized for size. figure 62 . circuit for heart rate measurement ne xt to h eart a shorter distance from the AD8232 to the heart makes this application l ess vulnerable to common - mode interference. however, since rld i s not used to drive an electrode, it can be used to improve the common - mode rejection by maintaining the midscale voltage through the 10 m bias resistors. a single - pole high - pass filter is set at 7 hz, and there is no low - pass filter . no gain is used on t he output op amp thereby reducing the number of resistors for a total system gain of 100. figure 63 . frequency r esponse for hrm next to heart circ uit the input terminals in this configuration use two 180 k resistor s, to protect the user from fault conditions. t wo 10 m resistors provide input bias . use higher values for electrodes with high output impedance, such as cloth electrodes. the schematic also shows two 10 m resistors to set t he midscale reference voltage. if there is already a reference voltage available, it can be driven into the refin input to eliminate the se two 10 m resistors. exercise application : heart rate measure d a t t he hands in this application, the heart rate signal is measured at the hands with s tainless steel electrodes. the users arm and upper body movement create large motion artifacts and the long lead length makes the system susceptible to common - mode inter - ference. a very narrow band - pass characteristic is required to separate the heart sig nal from the interferers. figure 64 . circuit for heart rate measurement at h ands the circuit in figure 64 uses a two - pole high - pass filter set at 7 hz. a two - pole low - pass filter at 2 4 hz follows the high - pass filters to eliminate any other artifacts and line noise. figure 65 . frequency r esponse for h rm c ircuit t aken at the h ands 10866-161 +v s +v s +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc sdn lo+ lo? rld rldfb out opamp+ opamp? refout sw AD8232 180k 180k 10m 10m 0.1f 10m 1nf 10m electrode interface 0.1f 0.22f to digital interface signal output 10m 70 0 0.1 10k magnitude (db) frequency (hz) 10866-057 10 20 30 40 50 60 1 10 100 1k 10866-262 rl ra la +v s +v s +v s +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc sdn lo+ lo? rld rldfb out opamp+ opamp? refout sw AD8232 22nf 1m 1m 100k 3.3nf 100k 180k 180k 1m 10m 10m 0.1f 10m 1nf 10m 10m 0.1f 360k 0.22f to digital interface signal output 0.22f 70 0 0.1 1k magnitude (db) frequency (hz) 10866-059 10 20 30 40 50 60 1 10 100
data sheet AD8232 rev. a | page 25 of 28 the overall narrow - band nature of this filter combination distorts the ecg waveform significantly. therefore, it is only suitable to determine the heart rate, and not to ana lyze the ecg signal characteristics. the low - pass filter stage also includes a gain of 11, to bring the total system gain close to 11 00 (note that the filter roll off prevents the maximum gain from reach ing this value) . because the ecg signal is measured at the hands, it is weaker than when measured closer to the heart. the rld circuit drives to the third electrode, which can also be located at the hands, to cancel common - mode interference. c ardiac m onitor c onfiguration this configuration is designed for m onitoring the shape of the ecg waveform. it assume s that the patient remains relatively still during the measurement, and therefore, motion artifacts are less of an issue. figure 66 . circuit for ecg waveform monitoring to obtain an ecg waveform with minim al distortion, the AD8232 is configured with a 0.5 hz two - pole high - pass filter followed by a two - pole , 40 hz , low - pass filter. a third electrode is driven for optimum common - mode rejection. figure 67 . fr equency r esponse of cardiac monitor circuit in addition to 40 hz filtering, the op amp stage is configured for a gain of 11 , resulting in a total syste m gain of 1100. to optimize the dynamic range of the system , the gain level is adjust able , depending on t he input signal amplitude (which may vary with electrode placement) and adc input range. p ortable c ardiac m onitor with e limina - tion of m otion a rtifacts the circuit in figure 68 shows an implementation of a battery - powered embedded system for monitoring heart rate in applications where the patient engages in moderate activ ity, such as with a holter monitor. the AD8232 uses a three - electrode patient interface and implements a two - pole high - pass filter with a cutoff at 0.3 hz , and a two - pole low - pass filter with a cutoff frequency of 37 hz . the total signa l gain in the pass band is 400 . the fully conditioned signal is sampled by the sigma - delta adc integrated on the low power microcontroller, aducm360 . the wide dynamic range of this adc provides flexibil ity to reduce the signal gain to a void saturation , depending on electrode placement. because the pass band is relatively wide for ambulatory applica - tions, t he adxl346 accelerometer signal can be used to further minimize the nois e introduced by the motion of the patient. moreover, the microcontroller can use the motion information to monitor inactivity and to issue a system shutdown to save battery power . the low dropout regulator ensures that the maximum of 3 v is not exceeded, especially during charge cycles of the battery, which can be a lithium - ion cell. in this application, the aducm360 uses its p ort 0 to perform dma transfers to the host communication interface or to an on - board memory , if recording the waveform for later transfer . however, in any particular application, this port should be used for the busiest interface to minimize cpu cycles and maintain low power operation. note that th is circuit is shown to demonstrate the capabilities of AD8232 and other system components. it is not a com plete system design and a dditional effort must be made to ensure compliance with medical safety guidelines from regulatory agencies. rl ra la +v s +v s +v s +in ?in hpdrive +v s hpsense iaout refin gnd fr ac/dc sdn lo+ lo? rld rldfb out opamp+ opamp? refout sw AD8232 10nf 1m 1m 100k 1.5nf 180k 180k 1m 10m 10m 0.1f 1nf 10m 10m 0.1f 360k 0.33f 0.33f refout 10m ? 1.4m ? to digital interface signal output 10866-266 10m 70 0 0.01 1k magnitude (db) frequency (hz) 10866-061 10 20 30 40 50 60 0.1 1 10 100
AD8232 data sheet rev. a | page 26 of 28 figure 68 . low power portable cardiac monitor 10866-163 ra la rl +v s +v s +v s hpsense iaout refin gnd fr ac/dc sdn lo+ lo? +in ?in hpdrive rld rldfb out opamp+ opamp? refout sw AD8232 6.8nf 1m 1m 332k 2.7nf 100k 180k 180k 1m 10m 10m 0.1f 10m 1nf 10m 10m 0.1f 360k 4.7f 4.7f +v s 1f 1f +v s 4.7f 0.47f 0.47f 1f v batt +v s adxl346 vs vddio gnd to host, memory or display +v s = +2.8v tx clk rx cs electrode interface p1.sclk0 p1.4/miso0 p1.6/mosi0 p0.1/sclk1 p0.2/mosi1 p0.0/miso1 p0.3/cs1 p0.6/irq2 p1.7/cs0 reg_dvdd avdd_reg aducm360 adp150x-2.8 gnd vin vout scl/sclk int2 sda/sdi/sdio sdo/alt_add cs ain0 ain1 p1.1 p1.0 p1.2 vref+ vref? iovdd gnd avdd
data sheet AD8232 rev. a | page 27 of 28 packaging and ordering information outline dimensions figure 69 . 20 - lead lead frame chip scale package [lfcsp_wq] 4 mm 4 mm body, very very thin quad (cp - 20 - 10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ad8 232 a cpz -r 7 ?40c to +85 c 20 - lead lead frame chip scale package [lfcsp_wq] cp -20 -10 ad8 232 a cpz -r l ?40c to +85 c 20 - lead lead frame chip scale package [lfcsp_wq] cp -20 -10 ad8 232 a cpz -wp ?40c to +85 c 20 - lead lead frame chip scale package [lfcsp_wq] cp -20 -10 AD8232 - evalz evaluation board 1 z = rohs compliant part. 0.50 bsc 0.50 0.40 0.30 0.30 0.25 0.20 compliant t o jedec standards mo-220-wggd. 061609-b b o t t o m v i e w t o p v i e w e x p o s e d p a d pin 1 indica t or 4.10 4.00 sq 3.90 sea ting plane 0.80 0.75 0.70 0.05 max 0.02 nom 0.20 ref 0.25 min coplanarity 0.08 pin 1 indic a t or 2.65 2.50 sq 2.35 for proper connection of the exposed pad, refer to the pin confi gurat ion and function descriptions section of this data sheet . 1 2 0 6 1 0 1 1 1 5 1 6 5
AD8232 data sheet rev. a | page 28 of 28 notes ? 2012 C 2013 analog devices, inc. all rights reserved. tradem arks and registered trademarks are the property of their respective owners. d10866 - 0- 2/13(a) www.analog.com/ AD8232

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